Digital Design Implementing 8085

All op codes are not represented / implemented in this design however adding them should be very straight forward. This digital design utilizes a bus in order to achieve high efficiency and throughput.  The design is scaled back a bit and uses less registers than the actual 8085.  This can be easily modified though.  Additional op-codes can also be added. Included in this post is are the .src (source) .fmt (format/debug) files. Note that the ‘cpu’ is reading op codes from memory not a .in file!

Click here for the full post including SLSL code.

- COMP-E

This entry was posted on Saturday, March 7th, 2009 at 7:30 pm and is filed under Verilog, comp-e, forum. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.

2 Responses to “Digital Design Implementing 8085”

  1. amit das on January 15th, 2010 at 10:38 am

    hi!!!

  2. COMP-E on January 28th, 2010 at 2:18 am

    hello : )

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