This SLSL / ‘sudo verilog’ program implements the digital design of a pipeline having multiple registers, an adder, and multiplication architecture. The program can easily be re-implemented in Verilog at your discretion. SLSL is a wonderful language that allows for rapid development of digital designs, which is why many of my programs are done in it. Conceptually, you can code from a block diagram to an HDL with it. Unfortunately SLSL is not available to the public, but it should be quite easy for anyone with a couple Verilog or VHDL programs under their belt to understand. The code can be found here.
COMP-E
~a place where computer engineers can play