 | Code: system proj4;
/* =============== Control =============== */
/* 0 1 2 3 4 5 6 7 8 9 */
/* ----------------------- */
/* |a| |b|a|c|b|d|c| |d| | */
/* ----------------------- */
/* | |a| |b|a|c|b|d|c| |d| */
/* ----------------------- */
/* + - + - + - + - + - + */
/* ============ Architecture ============*/
register R1[11], R2[11], R3[11], T1[11], R_in[4], R_out[11];
register cntr_state, in_clk, out_clk;
wire A[4], B[7], Mult_Result[11];
wire _S1[6], _C1[6], _S2[6], _C2[6], _S3[6], _C3[6], _S4[6], _C_OUT;
wire port1[4], sum[11], c_out, sub, port2[11];
begin
CSA(andgate(a[0], b[6..1]), andgate(a[1], b[5..0]), 0:6, _S1, _C1);
CSA(andgate(a[2], b[5..0]), {a[1]*b[6], _S1[5..1]}, _C1, _S2, _C2);
CSA(andgate(a[3], b[5..0]), {a[2]*b[6], _S2[5..1]}, _C2, _S3, _C3);
CPA({a[3]*b[6], _S3[5..1]}, _C3, 0:1, _S4, _C_OUT);
Mult_Result := {_C_out, _S4, _S3[0], _S2[0], _S1[0], a[0]*b[0]};
CPA(T1, xorgate(sub,mux(~cntr_state, 7:11, 3:11)), sub, sum, c_out);
R_in, in_clk*clock := port1; /* in_clk * clock is effectively a mod 2 counter */
R_out, out_clk*clock := sum;
R1, clock := sum;
R2, clock := R1;
R3, clock := R2;
T1, ~clock := Mult_result;
port2 := R_out;
a := mux(cntr_state, port1, R_in);
b := mux(cntr_state, 5:7, R3[6..0]);
end;
begin
cntr_state, clock := ~cntr_state;
out_clk, ~clock := cntr_state;
in_clk, ~clock := cntr_state;
sub := ~cntr_state;
end;
begin
read("proj4.in", in_clk*clock, port1);
trace := clock;
end.
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