 | Code: system proj3;
register r_a[6], r_b[6], r_c[6], r_d[6], r_x[6];
register r_stepCount[2] = 0, r_ir[6], r_pc[4] = 0;
wire w_stepCount[4], w_ir[6], w_pc[4];
wire w_a_ts, w_b_ts, w_c_ts, w_d_ts, w_x_ts,
w_my_ram_ts, w_alu_cout, w_alu_addsub;
wire w_add, w_sub, w_mov, w_nop, w_lda, w_sta, w_xch;
wire w_a1, w_b1, w_c1, w_d1,
w_a2, w_b2, w_c2, w_d2;
wire w_alu_sum[6], w_bus[6], w_memaddr[4], w_regA[6];
wire w_ram_mux0, w_regA_mux0, w_reset;
register r_stateA, r_stateB, r_stateC, r_stateD, r_stateF,
r_stateG, r_stateE1, r_stateE2, r_stateE3;
memory my_ram(4)[6] = { 44, 20, 45, 51, 46, 24, 54, 10, 5, 11, 15, 0, 12, 7, 10, 3 };
/* control */
begin
trace := clock;
/* PCounter Setup */
w_pc := r_pc;
/* Instruction Decoding */
w_ir := r_ir;
/* MUX Setup */
w_regA_mux0 := r_stateB + r_stateC;
w_ram_mux0 := ~r_stateA;
w_regA := mux(w_regA_mux0, w_bus, w_alu_sum);
w_memaddr := mux(w_ram_mux0, w_pc, w_ir[3..0]);
/* Counter Setup */
r_stepCount, ~clock := mux(w_reset,inc(r_stepCount), 0:2);
w_stepCount := decode(r_stepCount);
w_reset := r_stateA*w_nop +
(w_stepCount[1] * ( w_add + w_sub + w_mov + w_lda + w_sta));
/* == OP Code Wires == */
w_add := ~w_ir[5] * ~w_ir[4] * ~w_ir[3] * w_ir[2];
w_sub := ~w_ir[5] * ~w_ir[4] * w_ir[3] * ~w_ir[2];
w_sta := ~w_ir[5] * ~w_ir[4] * w_ir[3] * w_ir[2];
w_mov := ~w_ir[5] * w_ir[4];
w_lda := w_ir[5] * ~w_ir[4];
w_xch := w_ir[5] * w_ir[4];
w_nop := ~w_add * ~w_sub * ~w_sta * ~w_mov * ~w_lda * ~w_xch;
/* == Register Select Wires == */
w_a1 := (w_mov + w_xch) * (~w_ir[3] * ~w_ir[2]);
w_b1 := (w_mov + w_xch) * (~w_ir[3] * w_ir[2]);
w_c1 := (w_mov + w_xch) * ( w_ir[3] * ~w_ir[2]);
w_d1 := (w_mov + w_xch) * ( w_ir[3] * w_ir[2]);
w_a2 := (w_mov + w_xch + w_add + w_sub) * (~w_ir[1] * ~w_ir[0]);
w_b2 := (w_mov + w_xch + w_add + w_sub) * (~w_ir[1] * w_ir[0]);
w_c2 := (w_mov + w_xch + w_add + w_sub) * ( w_ir[1] * ~w_ir[0]);
w_d2 := (w_mov + w_xch + w_add + w_sub) * ( w_ir[1] * w_ir[0]);
/* == State Wires == */
r_stateA, ~clock := w_stepCount[0] + w_nop;
r_stateB, ~clock := w_stepCount[1] * w_add;
r_stateC, ~clock := w_stepCount[1] * w_sub;
r_stateD, ~clock := w_stepCount[1] * w_mov;
r_stateE1, ~clock := w_stepCount[1] * w_xch;
r_stateE2, ~clock := w_stepCount[2] * w_xch;
r_stateE3, ~clock := w_stepCount[3] * w_xch;
r_stateF, ~clock := w_stepCount[1] * w_lda;
r_stateG, ~clock := w_stepCount[1] * w_sta;
/* == Tristate Wires == */
w_a_ts := (r_stateB*w_a2) + (r_stateC*w_a2) + (r_stateG) +
(r_stateD*w_a2) + (r_stateE1*w_a1) + (r_stateE2*w_a2);
w_b_ts := (r_stateB*w_b2) + (r_stateC*w_b2) +
(r_stateD*w_b2) + (r_stateE1*w_b1) + (r_stateE2*w_b2);
w_c_ts := (r_stateB*w_c2) + (r_stateC*w_c2) +
(r_stateD*w_c2) + (r_stateE1*w_c1) + (r_stateE2*w_c2);
w_d_ts := (r_stateB*w_d2) + (r_stateC*w_d2) +
(r_stateD*w_d2) + (r_stateE1*w_d1) + (r_stateE2*w_d2);
w_x_ts := r_stateE3;
w_my_ram_ts := r_stateF + r_stateA;
w_alu_addsub := r_stateC;
end;
/* architecture */
begin
/* Bus Setup */
w_bus := busfunc( w_a_ts, r_a, w_b_ts, r_b, w_c_ts, r_c, w_d_ts, r_d,
w_x_ts, r_x, w_my_ram_ts, my_ram(w_memaddr));
/* ALU Setup */
CPA(r_a, xorgate(w_alu_addsub, w_bus), w_alu_addsub, w_alu_sum, w_alu_cout);
/* Increment the Program Counter */
r_pc, clock*r_stateA := inc(r_pc);
/* Instruction Fetch */
r_ir, clock*r_stateA := w_bus;
/* Register Gets Clocked */
r_a, clock*(r_stateF + w_a1*(r_stateE2 + r_stateD) + w_a2*r_stateE3 + r_stateB + r_stateC) := w_regA;
r_b, clock*(w_b1*(r_stateE2 + r_stateD) + w_b2*r_stateE3) := w_bus;
r_c, clock*(w_c1*(r_stateE2 + r_stateD) + w_c2*r_stateE3) := w_bus;
r_d, clock*(w_d1*(r_stateE2 + r_stateD) + w_d2*r_stateE3) := w_bus;
r_x, clock*(r_stateE1) := w_bus;
/* Memory Write */
my_ram(w_memaddr), clock*r_stateG := w_bus;
end.
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