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Verilog - 4 to 1 and 2 to 1 multiplexor 
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Joined: Sat Jan 24, 2009 3:56 pm
Posts: 32
Post Verilog - 4 to 1 and 2 to 1 multiplexor
These two code snippets are for a 16-bit multiplexer and should be fairly straight forward so please pardon the lack of comments : )

2 to 1
Code:
module mux2g #(parameter N = 16)
(
   input wire [N-1:0] a,
   input wire [N-1:0] b,
   input wire s;
   output reg [N-1:0] z
);

always @(*)
   if(s == 0)
      z = a;
   else
      z = b;

endmodule


4 to 1
Code:
module mux4g #(parameter N = 16)
(
   input wire [N-1:0] a,
   input wire [N-1:0] b,
   input wire [N-1:0] c,
   input wire [N-1:0] d,
   input wire [1:0] s,
   output reg [N-1:0] z
);

   always @ (*)
      case (s)
         0:   z = a;
         1: z = b;
         2: z = c;
         3: z = d;
         default: z = a;
      endcase
endmodule


Thu Aug 06, 2009 6:57 am
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