Code: module mux4g #(parameter N = 16) ( input wire [N-1:0] a, input wire [N-1:0] b, input wire [N-1:0] c, input wire [N-1:0] d, input wire [1:0] s, output reg [N-1:0] z );
always @ (*) case (s) 0: z = a; 1: z = b; 2: z = c; 3: z = d; default: z = a; endcase endmodule
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