Tag Archives: FPGA

Verilog Examples For The Spartan 3 / Nexys 2 Boards

Well, I thought I’d be extra generous since I haven’t posted in so long, and have uploaded 4 verilog examples for your viewing pleasure. I have been a bit busy to comment them but I hope that they may be … Continue reading

Posted in Verilog, comp-e, forum | Tagged , , , , | Leave a comment

Calculate Min Max and Average Using Assembly

This assembly program reads in 8, 8-bit numbers and is able to calculate the min, max, and average of those numbers.  The code has been optimized for speed, but if compact code is what you want, by all means use … Continue reading

Posted in Assembly, comp-e, forum | Tagged , , , , | Leave a comment

Digital Design with Pipeline 6 Bit Registers

This SLSL / ‘sudo verilog’ program implements the digital design of a pipeline having multiple registers, an adder, and multiplication architecture. The program can easily be re-implemented in Verilog at your discretion. SLSL is a wonderful language that allows for … Continue reading

Posted in Verilog, comp-e, forum | Tagged , , , , , | Leave a comment

Nexys 2 Spartan 3 FPGA Arrives

It took a week to get it from Washington state, but it’s finally here.  My gorgeous Nexys 2 board I ordered from Digilent.  It uses the Xilinx Spartan 3-e chip and has a lot of nice extra features that the … Continue reading

Posted in Verilog, comp-e, forum | Tagged , , , , , , , , | 1 Comment

FPGAs!!!

Howdy all, I’ve been getting into some realy hobby stuff as of late and you will be seeing some forum posts on it in the near future.  I just got myself a Nexys 2 board ( Xilinx Spartan 3 – … Continue reading

Posted in comp-e, forum | Tagged , , , | Leave a comment