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	<title>comp-e.com &#187; Verilog</title>
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	<link>http://comp-e.com</link>
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		<title>Verilog Examples For The Spartan 3 / Nexys 2 Boards</title>
		<link>http://comp-e.com/verilog-examples-for-the-spartan-3-nexys-2-boards</link>
		<comments>http://comp-e.com/verilog-examples-for-the-spartan-3-nexys-2-boards#comments</comments>
		<pubDate>Thu, 06 Aug 2009 07:07:19 +0000</pubDate>
		<dc:creator>COMP-E</dc:creator>
				<category><![CDATA[Verilog]]></category>
		<category><![CDATA[comp-e]]></category>
		<category><![CDATA[forum]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Nexys 2]]></category>
		<category><![CDATA[Spartan3]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://comp-e.com/?p=135</guid>
		<description><![CDATA[Well, I thought I&#8217;d be extra generous since I haven&#8217;t posted in so long, and have uploaded 4 verilog examples for your viewing pleasure.
I have been a bit busy to comment them but I hope that they may be useful still as just coding examples.
Enjoy
Verilog &#8211; 14-bit BCD ( Binary Converted to Decimal)
Verilog &#8211; 4 [...]]]></description>
			<content:encoded><![CDATA[<p>Well, I thought I&#8217;d be extra generous since I haven&#8217;t posted in so long, and have uploaded 4 verilog examples for your viewing pleasure.</p>
<p>I have been a bit busy to comment them but I hope that they may be useful still as just coding examples.</p>
<p>Enjoy</p>
<p><a class="topictitle" title="Posted: Thu Aug 06, 2009 6:59 am" href="../forum/viewtopic.php?f=8&amp;t=41">Verilog &#8211; 14-bit BCD ( Binary Converted to Decimal)</a><br />
<a class="topictitle" title="Posted: Thu Aug 06, 2009 6:57 am" href="../forum/viewtopic.php?f=8&amp;t=40">Verilog &#8211; 4 to 1 and 2 to 1 multiplexor</a><br />
<a class="topictitle" title="Posted: Thu Aug 06, 2009 6:53 am" href="../forum/viewtopic.php?f=8&amp;t=39">Verilog &#8211; Seven Segment Display on Spartan 3 Board</a><br />
<a class="topictitle" title="Posted: Thu Aug 06, 2009 6:50 am" href="../forum/viewtopic.php?f=8&amp;t=38">Verilog &#8211; Simle PB Debounce Code For Spartan 3 Boards</a></p>
<p>- comp-e</p>
]]></content:encoded>
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		</item>
		<item>
		<title>Digital Design with Pipeline 6 Bit Registers</title>
		<link>http://comp-e.com/digital-design-with-pipeline-6-bit-registers</link>
		<comments>http://comp-e.com/digital-design-with-pipeline-6-bit-registers#comments</comments>
		<pubDate>Thu, 12 Mar 2009 22:33:55 +0000</pubDate>
		<dc:creator>COMP-E</dc:creator>
				<category><![CDATA[Verilog]]></category>
		<category><![CDATA[comp-e]]></category>
		<category><![CDATA[forum]]></category>
		<category><![CDATA[CE]]></category>
		<category><![CDATA[coding]]></category>
		<category><![CDATA[computer engineering]]></category>
		<category><![CDATA[FPGA]]></category>

		<guid isPermaLink="false">http://comp-e.com/?p=91</guid>
		<description><![CDATA[This SLSL / &#8217;sudo verilog&#8217; program implements the digital design of a pipeline having multiple registers, an adder, and multiplication architecture.  The program can easily be re-implemented in Verilog at your discretion.  SLSL is a wonderful language that allows for rapid development of digital designs, which is why many of my programs are [...]]]></description>
			<content:encoded><![CDATA[<p>This SLSL / &#8217;sudo verilog&#8217; program implements the digital design of a pipeline having multiple registers, an adder, and multiplication architecture.  The program can easily be re-implemented in Verilog at your discretion.  SLSL is a wonderful language that allows for rapid development of digital designs, which is why many of my programs are done in it.  Conceptually, you can code from a block diagram to an HDL with it.  Unfortunately SLSL is not available to the public, but it should be quite easy for anyone with a couple Verilog or VHDL programs under their belt to understand.  The code can be found <a title="Digital Design with Pipelined 6 Bit Registers" href="http://comp-e.com/forum/viewtopic.php?f=8&amp;t=18">here</a>.</p>
<p>COMP-E<br />
~a place where computer engineers can play</p>
]]></content:encoded>
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		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Nexys 2 Spartan 3 FPGA Arrives</title>
		<link>http://comp-e.com/nexys-2-spartan-3-fpga-arrives</link>
		<comments>http://comp-e.com/nexys-2-spartan-3-fpga-arrives#comments</comments>
		<pubDate>Sat, 07 Mar 2009 19:40:22 +0000</pubDate>
		<dc:creator>COMP-E</dc:creator>
				<category><![CDATA[Verilog]]></category>
		<category><![CDATA[comp-e]]></category>
		<category><![CDATA[forum]]></category>
		<category><![CDATA[CE]]></category>
		<category><![CDATA[coding]]></category>
		<category><![CDATA[computer engineering]]></category>
		<category><![CDATA[ece]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Nexys 2]]></category>
		<category><![CDATA[Spartan3]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://comp-e.com/?p=80</guid>
		<description><![CDATA[It took a week to get it from Washington state, but it&#8217;s finally here.  My gorgeous Nexys 2 board I ordered from Digilent.  It uses the Xilinx Spartan 3-e chip and has a lot of nice extra features that the one that Xilinx makes didn&#8217;t have.  Digilent&#8217;s website also has a ton of cool addons [...]]]></description>
			<content:encoded><![CDATA[<p>It took a week to get it from Washington state, but it&#8217;s finally here.  My gorgeous Nexys 2 board I ordered from Digilent.  It uses the Xilinx Spartan 3-e chip and has a lot of nice extra features that the one that Xilinx makes didn&#8217;t have.  Digilent&#8217;s website also has a ton of cool addons for the board which I hope to get when there&#8217;s some money to spare.   I&#8217;m going to start out slow and try and reacquaint myself a bit with verilog.   My intent is to make a simple calculator and then perhaps move to converting my SLSL code for the 8085 over to verilog.  The Nexys 2 board does come with some cool peripherals such as a ps2 port so I may get sidetracked and see what I can do if I hook up an old ball mouse too it.  I&#8217;ll try to keep you all posted here so the RSS grabs it, but check the forum for code postings and photos.  I&#8217;ll try to include links as things crop up.</p>
<p>- COMP-E</p>
]]></content:encoded>
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		</item>
		<item>
		<title>Digital Design Implementing 8085</title>
		<link>http://comp-e.com/digital-design-implementing-8085</link>
		<comments>http://comp-e.com/digital-design-implementing-8085#comments</comments>
		<pubDate>Sat, 07 Mar 2009 19:30:37 +0000</pubDate>
		<dc:creator>COMP-E</dc:creator>
				<category><![CDATA[Verilog]]></category>
		<category><![CDATA[comp-e]]></category>
		<category><![CDATA[forum]]></category>
		<category><![CDATA[CE]]></category>
		<category><![CDATA[coding]]></category>
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		<guid isPermaLink="false">http://comp-e.com/?p=78</guid>
		<description><![CDATA[All op codes are not represented / implemented in this design however adding them should be very straight forward. This digital design utilizes a bus in order to achieve high efficiency and throughput.  The design is scaled back a bit and uses less registers than the actual 8085.  This can be easily modified though.  Additional [...]]]></description>
			<content:encoded><![CDATA[<p>All op codes are not represented / implemented in this design however adding them should be very straight forward. This digital design utilizes a bus in order to achieve high efficiency and throughput.  The design is scaled back a bit and uses less registers than the actual 8085.  This can be easily modified though.  Additional op-codes can also be added. Included in this post is are the .src (source) .fmt (format/debug) files. Note that the &#8216;cpu&#8217; is reading op codes from memory not a .in file!</p>
<p>Click <a title="Creating the 8085 using SLSL" href="http://comp-e.com/forum/viewtopic.php?f=8&amp;t=19">here</a> for the full post including SLSL code.</p>
<p>- COMP-E</p>
]]></content:encoded>
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		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>FPGAs!!!</title>
		<link>http://comp-e.com/fpga</link>
		<comments>http://comp-e.com/fpga#comments</comments>
		<pubDate>Tue, 03 Mar 2009 17:01:39 +0000</pubDate>
		<dc:creator>COMP-E</dc:creator>
				<category><![CDATA[comp-e]]></category>
		<category><![CDATA[forum]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Spartan3]]></category>
		<category><![CDATA[Verilog]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://comp-e.com/?p=69</guid>
		<description><![CDATA[Howdy all,
I&#8217;ve been getting into some realy hobby stuff as of late and you will be seeing some forum posts on it in the near future.  I just got myself a Nexys 2 board ( Xilinx Spartan 3 &#8211; based) and will be seeing what I can get out of it.  The overall goal is [...]]]></description>
			<content:encoded><![CDATA[<p>Howdy all,</p>
<p>I&#8217;ve been getting into some realy hobby stuff as of late and you will be seeing some forum posts on it in the near future.  I just got myself a Nexys 2 board ( Xilinx Spartan 3 &#8211; based) and will be seeing what I can get out of it.  The overall goal is to write some verilog to create the 8085 for it and then from that make a &#8216;quad&#8217; 8085 <img src='http://comp-e.com/wp-includes/images/smilies/icon_biggrin.gif' alt=':D' class='wp-smiley' />   So, we&#8217;ll see how it goes you can check out my updated progress on this page and the FPGA directory on the comp-e forum which you can check out <a title="FPGA's" href="http://comp-e.com/forum/viewforum.php?f=41&amp;sid=0f197b70e292bec7a4950336a813c167">here</a>.</p>
<div id="attachment_75" class="wp-caption aligncenter" style="width: 310px"><img class="size-medium wp-image-75" title="nexys2_spartan3_board" src="http://comp-e.com/wp-content/uploads/2009/03/nexys2_4001-300x273.jpg" alt="Nexys 2: Spartan 3 board" width="300" height="273" /><p class="wp-caption-text">Nexys 2: Spartan 3 board</p></div>
<p>Cheers,</p>
<p>- COMP-E</p>
]]></content:encoded>
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